@inproceedings{3t1d-cache,
author = {Xiaoyao Liang and Ramon Canal and Gu-yeon Wei and David Brooks},
title = {{Process Variation Tolerant 3T1D-Based Cache Architectures}},
booktitle = {MICRO},
year = {2007},
}

@article{M5,
author = {Nathan L. Binkert and Ronald G. Dreslinski and Lisa R. Hsu and Kevin T. Lim and Ali G. Saidi and Steven K. Reinhardt},
title = {{The M5 Simulator: Modeling Networked Systems}},
journal ={IEEE Micro},
volume = {26},
issn = {0272-1732},
year = {2006},
pages = {52-60},
}

@phdthesis{ bienia11benchmarking,
  author = {Christian Bienia},
  title = {Benchmarking Modern Multiprocessors},
  school = {Princeton University},
  year      = {2011},
  month     = {January}
}

@inproceedings{cache-decay-2001,
 author = {Kaxiras, Stefanos and Hu, Zhigang and Martonosi, Margaret},
 title = {Cache decay: exploiting generational behavior to reduce cache leakage power},
 booktitle = {ISCA},
 year = {2001},
}

@inproceedings{mram-noc,
 author = {Mishra, Asit K. and Dong, Xiangyu and Sun, Guangyu and Xie, Yuan and Vijaykrishnan, Narayanan and Das, Chita R},
 title = {{Architecting On-Chip Interconnects for Stacked 3D STT-RAM Caches in CMPs}},
 booktitle = {ISCA},
 year = {2011},
}

@article{3T-Brooks,
  author    = {Xiaoyao, Liang and
               Ramon, Canal and
               Gu-Yeon, Wei and
               David, Brooks},
  title     = {{Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache
               to Combat Process Variability}},
  year      = {2008},
}



@inproceedings{multi-level-retention,
 author = {Zhenyu Sun and Xiuyuan Bi and Hai Li and Weng-Fai Wong and Zhong-liang Ong and Xiaochun Zhu and Wenqing Wu},
 title = {{Multi Retention Level STT-RAM Cache Designs with a Memristor-controlled Refresh Scheme}},
 booktitle = {to appear in MICRO},
 year = {2011},
}


